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- Samsung’s 3x DDR3 SDRAM – 4F2 or 6F2? You Be the Judge. .
In order to decrease cell area, companies came out with the first 6F 2 cells in 2007; this 6F 2 architecture is now used by all major players in the DRAM market The guys at ICInsights published the plot below in the latest McLean report which nicely illustrates the progress:
- Abstract - University of California, Berkeley
For DRAM technology, a double-gate array having vertical channel structure (DGVC) with 4F2 cell size is proposed, which can be fabricated on a bulk silicon wafer using the conventional memory process flow for stand-alone DRAM application The operation and scalability of the DGVC cell are demonstrated via TCAD device simulations
- 6F2 DRAM Cell layout 개발한지가 벌써 10년 전이라니…. . – go2origin
아래는 8F2와 6F2 의 간단 비교입니다 언뜻보시면 비슷해보이는데, unit cell의 크기를 보시면 차이가 남을 아실수 있습니다 위의 6F2 그림은 마이크론 특허 layout입니다 각회사마다 저마다의 6F2 layout을 개발해서 적용하고있습니다
- The Memory Hierarchy - University of California, San Diego
F2 (F-squared) is the smallest 2D feature we can manufacture • A single bit of a given type of memory (e g , SRAM or DRAM) requires a fixed number of F2 This number doesn’t change with process technology e g , NAND flash memory is 4F2 in 90nm and in 22nm
- Value Creator TED :: Samsung Tech Conference 2006 (2D pattern Design . . .
For a specific case of the Dynamic Random Access Memory (DRAM) active pattern, a general trend to use efficiently the space is the rearrangement and modification of the layout By adopting 6F2 cell design instead of conventional 8F2, we can obtain a reduction in the cell area by 20% [1]
- Schematics showing three DRAM cell structures - KNU
Schematics showing three DRAM cell structures • In the case of a planar capacitor structure, excessively large area is needed to satisfy the requirement of storage capacitance per cell (typical value is 25~30 fF) • Since the generation of 4Mb DRAM, trench capacitor or stacked capacitor structure has been
- Understanding DRAM Architecture - IIT Kanpur
•JEDEC Spec: At normal temp, cell retention time limit is 64ms At high (extended) temp, retention time halves to 32ms •The memory controller issues refresh operations periodically
- 8F2, 6F2 and 4F2 - globalsino. com
Comparing with 6F 2, due to larger cell size, the 8F 2 layout has two major advantages: i) The noise immunity is higher ii) The process complexity is lower However, 6F 2 cells can be used to decrease cell area with the same WL and BL pitchs
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