安裝中文字典英文字典辭典工具!
安裝中文字典英文字典辭典工具!
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- Ultrascle Kintex PLLE3_ADV no derived clock at all
Hello, In my design, i have a PLLE3_ADV with an input clock but i never get derived clocks at the outut of PLL3_ADV My design target an kintex ultrascale (xcku040-ffva1156-1-c) and i'm using Vivado 2018 3 Could, someone, confirm this strange behavior because i would expect derived clocks like with MMCM Regards, Cédric
- XC7Z035 的GMII 接口通过PL的 EMIO 扩展成千兆网口，PHY芯片用的是88E1111芯片，MAC怎么给PHY芯片提供125MH . . .
可由PL端的10M经MMCM产生。 问题2：PHY芯片88E1111一个管脚本身可以产生125M的时钟输出，我是否可以把这个125MHz时钟接到PL上，然后PL内部回环输出给PHY芯片的GTX_CLK，是不是这个相当于MAC给PHY芯片的125M时钟？ ANS：可以的。
- Widget - Xilinx Support
So using the MMCM (b) to remove the clock uncertaintly will help - it isn't easy to tell by how much from the datasheet - you need to implement it and ask the tool This probably will make it possible to generate the data with the required uncertainty (and you can use the phase shift of the MMCM to get the relationship you need)
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